1. Field of the Invention
The present invention relates to a method for production of a semiconductor device, and particularly to a method for production of a semiconductor device having a self-aligned contact structure.
2. Description of the Related Art
Semiconductor integrated circuit devices are under enhancement of speeds of transistors due to reduction of a parasitic capacitance and miniaturization of wirings for reduction of a production cost per unit element.
However, if the gate length of an MOS field effect transistor (MOSFET) decreases (particularly to 0.35 μm or less), a problem of a deterioration in transistor characteristics resulting from an increase in resistance of a wiring (gate electrode) or a parasitic resistance of a source/drain diffusion layer occurs. Therefore, a silicide gate is used for the purpose of reducing a wiring resistance.
In a logic type semiconductor integrated circuit device, a salicide (self-aligned silicide) structure in which a silicide is formed in a self-aligned manner on a gate electrode and a source/drain diffusion layer for reduction of a resistance is applied.
For increasing a density, a technique of self-aligned contact (hereinafter referred to as “SAC”) is applied when forming a contact connected to a diffusion layer shared by mutually adjacent elements in a DRAM (dynamic random access memory).
In recent years, the wiring has been further miniaturized, and in the DRAM, a material having a resistance lower than that of a tungsten silicide that has been previously used is needed.
In the logic type semiconductor integrated circuit device, the titanium silicide that has been previously used undergoes an increase in resistance due to occurrence of coagulation resulting from miniaturization of the wiring, and therefore development of a technique of using a cobalt silicide and a nickel silicide is underway.
The production process of the DRAM has the following problems in addition to the problems described above.
In the DRAM, the impurity concentration of the source/drain diffusion layer is reduced for inhibition of a short channel effect and alleviation of a drain field, and therefore the diffusion layer is so thin that there is a possibility that silicide formation increases a leak current. When a silicide layer is formed on a gate electrode by a process of forming a salicide structure (hereinafter referred to as “salicide process”), an etching stopper insulating film for formation of a SAC structure cannot be selectively provided just above the gate electrode. From these considerations, it has been difficult to apply the conventional salicide process directly to the production process of the DRAM having an SAC structure.
Methods for forming the SAC structure and the salicide structure will be described in detail below using the drawings.
FIGS. 5 to 8 are schematic sectional views for explaining a process of formation of the SAC structure (hereinafter referred to as “SAC process”) disclosed in Japanese Patent Laid-Open No. 9-293689.
In the DRAM, in a pair of adjacent FETs (field effect transistors), each FET shares one of a pair of diffusion layers which is between FETs, and a contact plug connected to this diffusion layer is formed by an SAC process. The other diffusion layer of each FET is connected to an electrode of a corresponding capacitance element.
FIG. 5 is an explanatory view of a process of forming a contact connecting a diffusion layer common in a pair of adjacent FETs to a wiring (bit line), and shown a state in which a resist pattern is formed on an interlayer insulating film for opening a contact hole in a self-aligned manner. A step to this point is carried out in a manner described below.
First, silicon substrate 41 (Si) subjected formation of wells and element isolation beforehand is prepared. On the surface of this substrate are formed gate electrodes 43 (polySi/WSix) via gate oxide films 42 (SiO2) formed by thermal oxidization. These gate electrodes 43 each have its top surface covered with offset oxide film 44 (SiOx) and its side surface covered with side wall 45 (SiOx). On the surface layer portion of silicon substrate 41, source/drain regions 46 having an LDD structure are formed in a self-aligned manner with respect to gate electrodes 43 and side walls 45. SiOx interlayer insulating film 47 is formed in a conformal form on the entire surface of the substrate. Here, the reason why SiOx interlayer insulating film 47 is formed not flatly but in a conformal form is that it is necessary to initially set a thickness of the interlayer insulating film so that a contact hole can be opened without necessity to carry out excess over-etching, since in this method, a selection ratio to underlying offset oxide film 44 and side wall 45 cannot be secured theoretically at a stage of etching for formation of the contact hole described later.
Next, on this film is formed resist pattern 48 (PR) by carrying out a photolithography step. The opening of resist pattern 48 is sufficiently large compared to a space between adjacent gate electrodes 43. Subsequently, SiOx interlayer insulating film 47 is dry-etched using resist pattern 48 as a mask. This etching is carried out until Si substrate 41 is exposed, so that contact hole 49 shown in FIG. 6 is formed.
As another method, there is a method in which the interlayer insulating film is flattened by using an etching stopping film. That is, as shown in FIG. 7, the steps until the patterning of gate electrodes 43 and offset oxide films 44 and the formation of side walls 45 are carried out as described above, and thereafter, the entire surface of the substrate is thinly coated with conformal SiN etching stopping film 50, followed by forming SiOx interlayer insulating film 51 to substantially flatten the entire surface. Next, on this film is formed resist pattern 52 (PR) by carrying out a photolithography step. The opening of resist pattern 52 is sufficiently large compared to a space between adjacent gate electrodes 43.
SiOx interlayer insulating film 51 is dry-etched using resist patter 52 as a mask. This etching is carried out under a condition allowing a high selection ratio to be achieved with respect to underlying SiN etching stopping film 50. The reason why SiOx interlayer insulating film 51 can be flattened is that even if over-etching is carried out in this stage, etching is stopped at the surface of SiN etching stopping film 50, and offset oxide film 44 and side wall 45 are protected. When SiN etching stopping film 50 is exposed, this film is then etched under a condition allowing a high selection ratio to be achieved with respect to offset oxide film 44 and side wall 45, so that contact hole 53 shown in FIG. 8 is completed.
FIGS. 9(a) to 9(d) and 10(a) to 10(c) are schematic sectional views for explaining a salicide process disclosed in Japanese Patent Laid-Open No. 7-183506.
An MOS transistor having a salicide structure is produced in a manner described below. First, gate oxide film 202 is formed on the surface of monocrystalline P type silicon substrate 201 having a (100) surface orientation. Polycrystalline silicon film 233 having a thickness of about 0.2 μm is deposited on the surface of gate oxide film 202 by a low pressure chemical vapor deposition (LPCVD) method. The temperature at which polycrystalline silicon film 233 is grown is about 600° C., and in film formation at this temperature, the film is formed as a polycrystalline film, and the obtained film is a polycrystalline silicon film in which (110) orientation is dominant. The grain size (diameter of crystal grain) of polycrystalline silicon film 233 at this stage is about 0.5 μm to 1.0 μm (see FIG. 9(a)).
Next, polycrystalline silicon film 233 is patterned using a publicly known lithography technique to form polycrystalline silicon film 233a. By ion implantation of an N type impurity using polycrystalline silicon film 233a as a mask, a low-concentration N type diffusion layer 235A is formed on the surface of P type silicon substrate 201. Thereafter, silicon oxide film 234 having a thickness of about 0.2 μm is deposited on the entire surface by the CVD method (see FIG. 9(b)).
Next, silicon oxide film 234 is subjected to anisotropic plasma etching, this silicon oxide film remains only on the side wall of polycrystalline silicon film 233a, and spacer 234a consisting of this silicon oxide film is formed. Ion implantation of an N type impurity is carried out using spacer 234a and polycrystalline film 233a as a mask, followed by carrying out lamp annealing to form a high-concentration N type diffusion layer 235B on the surface of P type silicon substrate 201 (surface of N type diffusion layer 235A). N type diffusion layer 235A and N type diffusion layer 235B form N type source/drain diffusion layer 235 of LDD type (see FIG. 9(c)). In this connection, polycrystalline silicon film 233a at this stage is a high-concentration N type film, but polycrystalline silicon film 233 at a film formation sage may be formed into an N-type film beforehand.
After the surface is cleaned with a fluoric acid, titanium film 236 having a desired thickness is deposited on the entire surface (see FIG. 9(d)).
Subsequently, a first heat treatment for a silicide formation reaction is carried out in an inert atmosphere or vacuum to form a titanium silicide film 237a on the surface of N type source/drain diffusion layer 235 and the surface of polycrystalline silicon film 233a. The crystal structure of the crystal grain of titanium silicide film 237a is a C49 structure. This heat treatment is carried out at 700° C. for about a second. At a higher temperature, inter-diffusion between silicon and titanium is so vigorous that formation of a titanium silicide film as a “layer” becomes difficult (see FIG. 10(a)).
Next, unreacted titanium film 236 is removed by a mixed aqueous solution of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) (see FIG. 10(b)).
Subsequently, a second heat treatment is carried out by lamp annealing at 800 to 900° C., so that titanium silicide layer 237a on the surface of polycrystalline silicon film 233a is converted into titanium silicide film 237ba and titanium silicide film 237a on the surface of N type source/drain diffusion layer 235 is converted into titanium silicide film 237bb. Consequently, gate electrode 238 consisting of N type polycrystalline silicon film 233a and titanium silicide film 237ba and source/drain region 239 consisting of N type source/drain diffusion layer 235 and titanium silicide film 237bb are obtained, and an N channel type MOS transistor having a salicide structure is formed. The crystal structure of the crystal grain of titanium silicide films 237ba and 237bb is a C54 structure, and the thickness of titanium silicide films 237ba and 237bb is about 30 to 35 nm (see FIG. 10(c)).
Techniques of forming a salicide structure using titanium silicide (TiSi2) formed by a reaction between titanium (Ti) and silicon (Si) as described above are widely applied according to miniaturization of the wiring.
However, further miniaturization of the wiring results in coagulation of titanium silicide, so that low-resistance titanium silicide is hard to be obtained. Accordingly, employment of cobalt silicide or nickel silicide, instead of titanium silicide, is under consideration.
Particularly in cobalt silicide (CoSi2), Co diffuses into Si and does not adsorb up Si as Ti does at the time of the silicide formation reaction between Ti and Si when cobalt silicide is formed by a silicide formation reaction between Co and Si, and therefore a short between silicide regions does not occur.
Cobalt silicide and nickel silicide have a low resistance, and are also preferable as a silicide material of the DRAM having an SAC structure. However, for cobalt silicide and nickel silicide, patterning by dry etching is difficult, and therefore it is difficult to form a gate pattern having a cobalt silicide layer or a nickel silicide layer on the upper layer side thereof.
When a silicide layer is formed on a gate electrode by the salicide process, an etching stopper insulating film for formation of the SAC structure cannot be selectively provided just above the gate electrode.
Therefore, a conventional SAC process could not be applied directly when forming the SAC structure having a silicide gate.